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Binary Reachability of Timed-register Pushdown Automata and Branching Vector Addition Systems

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dc.affiliationUniwersytet Warszawski
dc.contributor.authorLasota, Sławomir
dc.contributor.authorClemente, Lorenzo
dc.contributor.authorMazowiecki, Filip
dc.contributor.authorLazić, Ranko
dc.date.accessioned2024-01-24T18:38:34Z
dc.date.available2024-01-24T18:38:34Z
dc.date.issued2019
dc.description.financeNie dotyczy
dc.description.number3
dc.description.volume20
dc.identifier.doi10.1145/3326161
dc.identifier.issn1529-3785
dc.identifier.urihttps://repozytorium.uw.edu.pl//handle/item/102302
dc.identifier.weblinkhttp://dl.acm.org/ft_gateway.cfm?id=3326161&ftid=2064379&dwn=1
dc.languageeng
dc.pbn.affiliationcomputer and information sciences
dc.relation.ispartofACM Transactions on Computational Logic
dc.relation.pages1-31
dc.rightsClosedAccess
dc.sciencecloudnosend
dc.titleBinary Reachability of Timed-register Pushdown Automata and Branching Vector Addition Systems
dc.typeJournalArticle
dspace.entity.typePublication